Product Summary

The 74HC595PW is a high-speed Si-gate CMOS device. It is pin compatible with low power Schottky TTL (LSTTL). The 74HC595PW is specified in compliance with JEDEC standard no. 7A. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. The 74HC595PW is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The 74HC595PW has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. The applications of the device include serial-to-parallel data conversion and remote control holding register.

Parametrics

74HC595PW absolute maximum ratings: (1)tPHL/tPLH, propagation delay at CL=15PF; VCC=5V: SHCP to Q7’: 16ns; STCP to Qn: 17ns; MR to Q7: 14 ns; (2)fmax, maximum clock frequency SHCP, STCP: 100MHz; (3)CI, input capacitance: 3.5pF; (4)CPD, power dissipation capacitance per package: 115pF.

Features

74HC595PW features: (1)8-bit serial input; (2)8-bit serial or parallel output; (3)Storage register with 3-state outputs; (4)Shift register with direct clear; (5)100 MHz (typ) shift out frequency; (6)Output capability: parallel outputs; bus driver; serial output; standard; (7)ICC category: MSI.

Diagrams

Image Part No Mfg Description Data Sheet Download Pricing
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74HC595PW
74HC595PW

NXP Semiconductors

Counter Shift Registers 8-BIT SHIFT REG W/OUTPUT LATCH

Data Sheet

Negotiable 
74HC595PW,112
74HC595PW,112

NXP Semiconductors

Counter Shift Registers 8-BIT SHIFT REG

Data Sheet

0-1: $0.10
1-25: $0.10
25-100: $0.08
100-250: $0.08
74HC595PW,118
74HC595PW,118

NXP Semiconductors

Counter Shift Registers 8BIT SHIFT REGISTER W/OUTPUT LATCH

Data Sheet

0-1: $0.10
1-25: $0.09
25-100: $0.08
100-250: $0.08