Product Summary

The 74LVCH16374ADL+112 is 16-bit edge-triggered flip-flop featuring separate D-type inputs with bus hold (74LVCH16374ADL+112 only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal. The flip-flop of the 74LVCH16374ADL+112 will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. When pin nOE of the 74LVCH16374ADL+112 is LOW, the contents of the flip-flops are available at the outputs.

Parametrics

74LVCH16374ADL+112 absolute aximum ratings: (1)VCC, supply voltage: -0.5 min. +6.5 V max.; (2)IIK, input clamping current: VI < 0 V -50 mA min.; (3)VI, input voltage: -0.5 min. +6.5 V max.; (4)IOK, output clamping current: VO > VCC or VO < 0 V ±50 mA max.; (5)VO, output voltage: output HIGH-or LOW-state -0.5 min. VCC + 0.5 V max.; (6)output 3-state [2] -0.5 min. +6.5 V max.; (7)IO, output current: VO = 0 V to VCC - ±50 mA max.; (8)ICC, supply current: - 100 mA max.; (9)IGND, ground current: -100 mA min.; (10)Tstg, storage temperature: -65 min. +150℃ max.

Features

74LVCH16374ADL+112 features: (1)5 V tolerant inputs/outputs for interfacing with 5 V logic; (2)Wide supply voltage range from 1.2 V to 3.6 V; (3)CMOS low power consumption; (4)Multibyte flow-through standard pin-out architecture; (5)Low inductance multiple supply pins for minimum noise and ground bounce; (6)Direct interface with TTL levels; (7)All data inputs have bus hold (74LVCH16374A only); (8)High-impedance outputs when VCC = 0 V; (9)Complies with JEDEC standard JESD8-B/JESD36; (10)ESD protection: HBM JESD22-A114F exceeds 2000 V; CDM JESD22-C101D exceeds 1000 V; (11)Specified from -40℃ to +85℃ and -40℃ to +125℃.

Diagrams

74LV00
74LV00

Other


Data Sheet

Negotiable 
74LV00BQ,115
74LV00BQ,115

NXP Semiconductors

Gates (AND / NAND / OR / NOR) 3.3V QUAD 2-INPUT

Data Sheet

0-1: $0.13
1-25: $0.11
25-100: $0.10
100-250: $0.08
74LV00D
74LV00D

Other


Data Sheet

Negotiable 
74LV00D,112
74LV00D,112

NXP Semiconductors

Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND

Data Sheet

0-1: $0.22
1-25: $0.18
25-100: $0.15
100-250: $0.12
74LV00D,118
74LV00D,118

NXP Semiconductors

Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND

Data Sheet

0-1: $0.08
1-25: $0.07
25-100: $0.07
100-250: $0.06
74LV00DB,112
74LV00DB,112

NXP Semiconductors

Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND

Data Sheet

0-1: $0.22
1-25: $0.18
25-100: $0.15
100-250: $0.12