GAL20V8A-15LVC

Product Summary

The GAL20V8A-15LVC is a Generic Array Logic. The GAL20V8A-15LVC combines a high performance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable logic and bipolar performance at significantly reduced power levels. The GAL20V8A-15LVC features 8 programmable Output Logic Macrocelts (OLMCs) allowing each TRI-STATER output to be configured by the user. Additionally, the GAL20V8A-15LVC is capable of emulating, in a lunctionat/luse map/parametric compatible device, the most popular 24-pin PALR device architectures.

Parametrics

GAL20V8A-15LVC absolute maximum ratings: (1)Supply Voltage (Vqc): -0.5V to + 7.0V; (2)Input Voltage: -2.5V to Vqc +1-0V; (3)Off-State Output Voltage: -2.5V to Voc +1.0V; (4)Output Current: ±100mA; (5)Storage Temperature: -66℃ to +150℃; (6)Ambient Temperature with Power Applied: -65℃ to +125℃; (7)Junction Temperature: -65℃ to +150℃; (8)Lead Temperature (Soldering, 10 seconds): 260℃; (9)ESD Tolerance: 500V.

Features

GAL20V8A-15LVC features: (1)High performance E2CMOS technology, 10 ns maximum propagation delay; fcLK = 62.5 MHz; 8 ns maximum from clock input to data output; TTL compatible 24 mA outputs; UltraMOSR III advanced CMOS technology; (2)36% reduction in power, 115 mA max Ice; (3)Electrically erasable cell technology, Reconfigurable logic; Reprogrammable cells; 100% tested/guaranteed 100% yields; High speed electrical erasure (<50 ms); 20 year data retention; (4)Eight output logic macrocells, Maximum flexibility for complex logic designs; Programmable output polarity; Also emulates 24-pin PAL devices with full function/ fuse map/parametric compatibility; (5)Preload and power-up reset of all registers, 100% functional testability; (6)Fully supported by National PLAN development software; (7)Security cell prevents copying logic; (8)Electronic signature for identification ; (9)Same JEDEC map as GAL20V8.

Diagrams