IRS2113STRPBF

low side driver, 16-SOIC, 10 V to 20 V, IRS2113STRPBF

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Price:: US $0.79~0.79 / piece [Get Latest Price]

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	US $0.79~0.79

PartNumber:: IRS2113STRPBF

Brand:: International Rectifier - IR | Pack: SOP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-07-13

From Other Seller

Part Number:IRS2113STRPBF
US $0.79 - 0.79
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Product Summary

The IRS2113STRPBF is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs of the IRS2113STRPBF are compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction.

Parametrics

IRS2113STRPBF absolute maximum ratings: (1)High side floating supply voltage: -0.3V to 620V; (2)High side floating supply offset voltage: VB-20V to VB+0.3V; (3)High side floating output voltage: VS-0.3V to VB+0.3V ; (4)Low side fixed supply voltage: -0.3V to 20V; (5)Low side output voltage: -0.3V to VCC+0.3V ; (6)Logic supply voltage: -0.3V to VSS+20V; (7)Logic supply offset voltage: VCC-20V to VCC+0.3V; (8)Logic input voltage (HIN, LIN, & SD): VSS-0.3V to VDD+0.3V; (9)Allowable offset supply voltage transient: 50V/ns; (10)Junction temperature: 150℃ ; (11)Storage temperature: -55℃ to +150℃ ; (12)Lead temperature (soldering, 10 seconds): 300℃.

Features

IRS2113STRPBF features: (1)Floating channel designed for bootstrap operation; (2)Fully operational to +500 V or +600 V; (3)Tolerant to negative transient voltage, dV/dt immune; (4)Gate drive supply range from 10 V to 20 V; (5)Undervoltage lockout for both channels; (6)3.3 V logic compatible; (7)Separate logic supply range from 3.3 V to 20 V; (8)Logic and power ground ±5V offset; (9)CMOS Schmitt-triggered inputs with pull-down; (10)Cycle by cycle edge-triggered shutdown logic; (11)Matched propagation delay for both channels; (12)Outputs in phase with inputs.