MPC8560CPX667LB

Product Summary

The MPC8560CPX667LB is an Integrated Processor integrating a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8560CPX667LB is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual.

Parametrics

MPC8560CPX667LB absolute maximum ratings: (1)Core supply voltage, VDD: –0.3 to 1.32V For devices rated at 667 and 833 MHz; –0.3 to 1.43V For devices rated at 1 GHz; (2)PLL supply voltage, AVDD: –0.3 to 1.32V For devices rated at 667 and 833 MHz; –0.3 to 1.43V For devices rated at 1 GHz.

Features

MPC8560CPX667LB features: (1)High-performance, 32-bit Book E–enhanced core that implements the Power Architecture; (2)32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data; (3)Memory management unit (MMU) especially designed for embedded applications; (4)Enhanced hardware and software debug support; (5)Performance monitor facility (similar to but different from the MPC8560 performance monitor; (6)High-performance RISC CPM operating at up to 333 MHz; (7)CPM software compatibility with previous PowerQUICC families; (8)One instruction per clock; (9)Executes code from internal ROM or instruction RAM ; (10)32-bit RISC architecture; (11)Tuned for communication environments: instruction set supports CRC computation and bit manipulation; (12)Internal timer; (13)Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller; (14)Handles serial protocols and virtual DMA.

Diagrams